Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

ABSTRACT

A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.

CLAIM TO DOMESTIC PRIORITY

The present application is a division of U.S. patent application Ser.No. 11/934,009, filed Nov. 1, 2007, and claims priority to the foregoingparent application pursuant to 35 U.S.C. §120.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to formation of solder bump structures onsemiconductor devices.

BACKGROUND OF THE INVENTION

Semiconductor devices are found in many products used in modern society.Semiconductors find applications in consumer items such asentertainment, communications, networks, computers, and household itemsmarkets. In the industrial or commercial market, semiconductors arefound in military, aviation, automotive, industrial controllers, andoffice equipment.

The manufacture of semiconductor devices involves formation of a waferhaving a plurality of die. Each die contains hundreds or thousands oftransistors and other active and passive devices performing a variety ofelectrical functions. For a given wafer, each die from the wafertypically performs the same electrical function. Front-end manufacturinggenerally refers to formation of the semiconductor devices on the wafer.The finished wafer has an active side containing the transistors andother active and passive components. Back-end manufacturing refers tocutting or singulating the finished wafer into the individual die andthen packaging the die for structural support and/or environmentalisolation.

One goal of semiconductor manufacturing is to produce a package suitablefor faster, reliable, smaller, and higher-density integrated circuits(IC) at lower cost. Flip chip packages or wafer level packages (WLP) areideally suited for ICs demanding high speed, high density, and greaterpin count. Flip chip style packaging involves mounting the active sideof the die facedown toward a chip carrier substrate or printed circuitboard (PCB). The electrical and mechanical interconnect between theactive devices on the die and conduction tracks on the carrier substrateis achieved through a solder bump structure comprising a large number ofconductive solder bumps or balls. The solder bumps are formed by areflow process applied to solder material deposited on contact pads,which are disposed on the semiconductor substrate. The solder bumps arethen soldered to the carrier substrate. The flip chip semiconductorpackage provides a short electrical conduction path from the activedevices on the die to the carrier substrate in order to reduce signalpropagation, lower capacitance, and achieve overall better circuitperformance.

The reliability and integrity of the interconnect structure is importantto testing, manufacturing yield, and longevity of the product while inservice. In some devices, a problem of cracking has been detected in thepassivation layer surrounding the solder bump after solder reflow. Thecracking has been attributed to degradation of the passivation layercaused by the chemical processes used during formation of the solderbumps. The cracking problem is especially noted during formation andremoval of dry film used to create the solder bumps.

A need exists for a solder bump structure with enhanced strength andreliability.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a semiconductor devicecomprising a substrate having a plurality of semiconductor devicesformed on a surface of the substrate. A contact pad is formed over thesubstrate in electrical contact with the semiconductor devices. An RDLis formed over the substrate in electrical contact with the contact pad.A passivation layer is formed over the substrate and RDL. A portion ofthe passivation layer is removed to expose the RDL. An adhesive layer isformed over the passivation layer and the exposed RDL. A barrier layeris formed over a first portion of the adhesive layer which is over theexposed RDL. The barrier layer is not formed over a second portion ofthe adhesive layer. A wetting layer is formed over the barrier layerwhich is over the first portion of the adhesive layer. The wetting layeris not formed over the second portion of the adhesive layer. A bump isformed over the wetting layer and barrier layer.

In another embodiment, the present invention is a semiconductor devicecomprising a substrate and passivation layer formed over the substrate.An adhesive layer is formed over the passivation layer. A barrier layeris formed over a first portion of the adhesive layer. The barrier layernot being formed over a second portion of the adhesive layer. A wettinglayer is formed over the barrier layer over the first portion of theadhesive layer. The wetting layer not being formed over the secondportion of the adhesive layer. An electrical interconnect is formed overthe wetting layer and barrier layer.

In another embodiment, the present invention is a semiconductor devicecomprising substrate and passivation layer formed over the substrate. Anadhesive layer is formed over the passivation layer. A wetting layer isformed over a first portion of the adhesive layer. The wetting layer notbeing formed over a second portion of the adhesive layer. An electricalinterconnect is formed over the wetting layer.

In another embodiment, the present invention is a semiconductor devicecomprising a substrate and passivation layer formed over the substrate.An adhesive layer is formed over the passivation layer. A barrier layeris formed over a first portion of the adhesive layer. The barrier layernot being formed over a second portion of the adhesive layer. Anelectrical interconnect is formed over the barrier layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flip chip semiconductor device with solder bumps providingelectrical interconnect between an active area of the die and a chipcarrier substrate;

FIG. 2 illustrates formation of an adhesive layer over the secondpassivation layer;

FIG. 3 illustrates formation of a barrier layer and wetting layer overthe adhesive layer;

FIG. 4 illustrates patterning the UBM structure prior to etchingportions of the barrier layer and wetting layer;

FIG. 5 illustrates removing portions of the barrier layer and wettinglayer in a region outside the UBM structure while leaving the adhesivelayer intact over the passivation layer;

FIG. 6 illustrates formation of dry film layer over the adhesive layer,which protects the passivation layer and the deposition of soldermaterial;

FIG. 7 illustrates reflow of the solder material to form solder bumpsand removal of dry film layer; and

FIG. 8 illustrates removal of the adhesive layer from the region outsidethe UBM structure.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the Figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

The manufacture of semiconductor devices involves formation of a waferhaving a plurality of die. Each die contains hundreds or thousands oftransistors and other active and passive devices performing one or moreelectrical functions. For a given wafer, each die from the wafertypically performs the same electrical function. Front-end manufacturinggenerally refers to formation of the semiconductor devices on the wafer.The finished wafer has an active side containing the transistors andother active and passive components. Back-end manufacturing refers tocutting or singulating the finished wafer into the individual die andthen packaging the die for structural support and/or environmentalisolation.

A semiconductor wafer generally includes an active front side surfacehaving semiconductor devices disposed thereon, and a backside surfaceformed with bulk semiconductor material, e.g., silicon. The active frontside surface contains a plurality of semiconductor die. The activesurface is formed by a variety of semiconductor processes, includinglayering, patterning, doping, and heat treatment. In the layeringprocess, semiconductor materials are grown or deposited on the substrateby techniques involving thermal oxidation, nitridation, chemical vapordeposition, evaporation, and sputtering. Patterning involves use ofphotolithography to mask areas of the surface and etch away undesiredmaterial to form specific structures. The doping process injectsconcentrations of dopant material by thermal diffusion or ionimplantation. The active surface is substantially planar and uniformwith electrical interconnects, such as bond pads.

Flip chip semiconductor packages and wafer level packages (WLP) arecommonly used with integrated circuits (ICs) demanding high speed, highdensity, and greater pin count. Flip chip style semiconductor device 10involves mounting an active area 12 of die 14 facedown toward a chipcarrier substrate or printed circuit board (PCB) 16, as shown in FIG. 1.Active area 12 contains active and passive devices, conductive layers,and dielectric layers according to the electrical design of the die. Theelectrical and mechanical interconnect is achieved through a solder bumpstructure 20 comprising a large number of individual conductive solderbumps or balls 22. The solder bumps are formed on bump pads 24, whichare disposed on active area 12. The bump pads 24 connect to the activecircuits by conduction tracks in active area 12. The solder bumps 22 areelectrically and mechanically connected to contact pads 26 on carriersubstrate 16 by a solder reflow process. The flip chip semiconductordevice provides a short electrical conduction path from the activedevices on die 14 to conduction tracks on carrier substrate 16 in orderto reduce signal propagation, lower capacitance, and achieve overallbetter circuit performance.

FIG. 2 illustrates a cross-sectional view of the formation of a supportstructure for a solder bump. Note that for FIGS. 2-8 the semiconductordevice is oriented with its active surface facing up. In FIG. 2, metalcontact pad 32 is formed on silicon substrate 34. Contact pad 32 is madeof aluminum (Al), copper (Cu), or aluminum/copper alloys. Contact pad 32is electrically connected to active and passive devices throughconduction tracks or layers formed on substrate 34. A solder bump willlater be formed to connect through an RDL to the metal contact pad. Afirst passivation layer 36 is formed over substrate 34 with an openingto expose metal contact pad 32. The opening is realized by removing aportion of passivation layer 36 through a photoresist mask definedetching process. The first passivation layer 36 can be made with siliconnitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON),polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or otherinsulating material.

A first redistribution layer (RDL) 40 is formed over first passivationlayer 36, as shown in FIG. 2. RDL 40 provides electrical contact betweenpad 32 and solder bump area 48 which is provided for the first solderbump. A second RDL 42 is also is formed over first passivation layer 36.RDL 42 provides electrical contact between other conduction tracks onsubstrate 34 and solder bump area 50 which is provided for the secondsolder bump. The first and second RDLs can be made with Aluminum (Al),Aluminum Copper alloy (AlCu), Cu, or Cu alloy. RDLs 40 and 42 operate asan intermediate conduction layer to route electrical signals to variousareas of the die, including active and passive circuits, and providesvarious electrical interconnect options during package integration.

A second passivation layer 44 is formed over first passivation layer 36and RDLs 40 and 42. The second passivation layer is thicker than RDLs 40and 42. In one embodiment, passivation layer 44 is about 5-15 μm inthickness and RDL 40 is about 1-3 μm in thickness. Passivation layer 44can be made using similar material as described for passivation layer36. In another embodiment, passivation layers 36 and 44 are formed byrepassivation. A portion of second passivation layer 44 is removed by aphotoresist mask defined etching process for the first and second solderbumps in areas 48 and 50 or the second passivation layer isphotosensitive and can be patterned directly.

An adhesive layer 46 is formed on passivation layer 44 and RDLs 40 and42. In one embodiment, adhesive layer 46 is about 200-2000 angstroms inthickness. Adhesive layer 46 can be titanium (Ti), Al, titanium tungsten(TiW), and chromium (Cr). Adhesive layer 46 is patterned to follow thecontour of passivation layer 44 and RDLs 40 and 42. Accordingly, theformation of adhesive layer 46 is depressed in solder bump areas 48 and50 and covers substantially the entire surface of passivation layer 44,particularly in and around areas 48 and 50, as seen in FIG. 2.

FIG. 3 illustrates a barrier layer 52 formed over adhesive layer 46, andwetting layer 54 formed over barrier layer 52. Barrier layer 52 andwetting layer 54, in combination with adhesive layer 46, forms an underbump metallization (UBM) in areas 48 and 50 for the first and secondsolder bumps. The adhesion layer 46 bonds to barrier layer 52. Barrierlayer 42 inhibits the diffusion of materials destructive to silicon suchas Cu into the active area of the die. Barrier layer 52 is optionaldepending on the materials used and the application. Wetting layer 52electrically connects to contact pad 32 via RDL 40. In one embodiment,barrier layer 52 is about 3000-4000 angstroms in thickness, and wettinglayer 54 is about 5000-10000 angstroms in thickness. Barrier layer 52can be made of nickel (Ni), Ni-alloy, platinum (Pt), palladium (Pd),TiW, and chromium copper (CrCu). Wetting layer 54 can be made with Cu,gold (Au), or Al. Barrier layer 52 is patterned to follow the contour ofadhesive layer 46. Likewise, wetting layer 54 is patterned to follow thecontour of barrier layer 52 and acts as an intermediate conduction layerformed between the first solder bump and RDL 40. The patterning barrierlayer 52 and wetting layer 54 and adhesive layer 46, as described above,define the solder bump areas 48 and 50 for forming solder bumps. Thebarrier layer 52 and wetting layer 54 and adhesive layer 46 enhancereliability of the bump support structure.

In FIG. 4, a photoresist layer is deposited over wetting layer 54. Thephotoresist layer is patterned to provide photoresist layers 56 and 58over solder bump areas 48 and 50, respectively. In FIG. 5, the portionsof barrier layer 52 and wetting layer 54, which are not protected byphotoresist layers 56 and 58, are removed using a wet etch process. Thatis, only the portions of wetting layer 54 and barrier layer 52 in theregion outside the UBM structure are etched away. The adhesive layer 46in the region outside the UMB structure remains in place at this stageof the process. As will be shown, the portion of adhesive layer 46 inthe region outside solder bump areas 48 and 50 protects passivationlayer 44 from chemical degradation during formation of the solder bumpsin later stages of the process. Photoresist layers 56 and 58 are thenremoved, leaving the UBM structure comprising adhesive layer 46, barrierlayer 52, and wetting layer 54 only in solder bump areas 48 and 50.

In FIG. 6, a dry film layer 60 is deposited over adhesive layer 46 andthe UBM structure comprising adhesive layer 46, barrier layer 52, andwetting layer 54. The dry film layer is patterned, and the portion ofthe dry film over the UBM structure is removed. Solder material 62 isdeposited over the UBM structure between the patterned dry film layerthrough a screen printing, or electrolytic plating or electrolessplating process. The solder material can be any metal or electricallyconductive material, e.g., tin (Sn), lead (Pb), Ni, Au, silver (Ag), Cu,bismuthinite (Bi) and alloys thereof, or mixtures of other electricallyconductive material. In one embodiment, the solder material is 63percent weight of Sn and 37 percent weight of Pb.

In FIG. 7, the solder material is reflowed by heating the conductivematerial above its melting point to form spherical balls or bumps 64 and66 over semiconductor substrate 34. In one embodiment, solder bumps 64and 66 are about 70˜180 μm in height. In some applications, solder bumps64 and 66 are reflowed a second time to improve electrical contact tothe UBM structure.

It is important to note that during the solder bump formation process,the adhesive layer 46 in the region outside the UBM structure remains inplace. The previous step of removing the portion of wetting layer 54 andbarrier layer 52 in the region outside the UBM structure did not involveadhesive layer 46. The adhesive layer 46 in the region outside the UBMstructure remains in place and protects passivation layer 44 againstchemical degradation during the formation of the solder bumps, inparticular during deposition and remove of dry film layer 60. Theadhesive layer over the passivation layer reduces cracking of thepassivation layer 44 without incurring additional manufacturing costs.

In FIG. 8, a wet etching process applied to remove any portion ofadhesion layer 46 in the region outside the region of the solder bumpstructure using solder bumps as the etching mask. Solder bump 64electrically contacts metal contact pad 32 by way of RDL 40. Likewise,solder bump 66 electrically contacts RDL 42.

In another embodiment, semiconductor device 10 can be made with a directcontact between the solder bump and the contact pad, i.e., without RDLsor other conductive routing structure. In this case, contact pad 32 isformed directly under the UBM structure. A similar process, as describedin FIGS. 2-8, would be used for the direct solder bump to contact padembodiment. The adhesive layer in the region outside the UBM structureprotects the passivation layer against chemical degradation duringformation of the solder bumps, particularly during deposition andremoval of dry film layer. Again, the adhesive layer over thepassivation layer reduces cracking of the passivation layer withoutincurring additional manufacturing costs.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A semiconductor device, comprising: a substrate having a plurality ofsemiconductor devices formed on a surface of the substrate; a contactpad formed over the substrate in electrical contact with thesemiconductor devices; a redistribution layer (RDL) formed over thesubstrate in electrical contact with the contact pad; a passivationlayer formed over the substrate and RDL, wherein a portion of thepassivation layer is removed to expose the RDL; an adhesive layer formedover the passivation layer and the exposed RDL; a barrier layer formedover a first portion of the adhesive layer which is over the exposedRDL, the barrier layer not being formed over a second portion of theadhesive layer; a wetting layer formed over the barrier layer which isover the first portion of the adhesive layer, the wetting layer notbeing formed over the second portion of the adhesive layer; and a bumpformed over the wetting layer and barrier layer.
 2. The semiconductordevice of claim 1, wherein the first portion of the adhesive layer isremoved after the bump is formed.
 3. The semiconductor device of claim1, wherein the wetting layer, barrier layer and adhesive layerconstitute an under bump metallization structure.
 4. The semiconductordevice of claim 1, wherein the adhesive layer follows a contour of thepassivation layer.
 5. A semiconductor device, comprising: a substrate; apassivation layer formed over the substrate; an adhesive layer formedover the passivation layer; a barrier layer formed over a first portionof the adhesive layer, the barrier layer not being formed over a secondportion of the adhesive layer; a wetting layer formed over the barrierlayer over the first portion of the adhesive layer, the wetting layernot being formed over the second portion of the adhesive layer; and anelectrical interconnect formed over the wetting layer and barrier layer.6. The semiconductor device of claim 5, further including a plurality ofsemiconductor devices formed on a surface of the substrate.
 7. Thesemiconductor device of claim 5, further including: a contact pad formedover the substrate; and a redistribution layer (RDL) formed over thesubstrate in electrical contact with the contact pad.
 8. Thesemiconductor device of claim 7, wherein the passivation layer is formedover the RDL and a portion of the passivation layer is removed to exposethe RDL.
 9. The semiconductor device of claim 8, wherein the barrierlayer is formed over the first portion of the adhesive layer which isover the exposed RDL.
 10. The semiconductor device of claim 5, whereinthe first portion of adhesive layer is removed after the bump is formed.11. The semiconductor device of claim 5, wherein the wetting layer,barrier layer and adhesive layer constitute an under bump metallizationstructure.
 12. The semiconductor device of claim 5, wherein the adhesivelayer follows a contour of the passivation layer.
 13. The semiconductordevice of claim 5, wherein the electrical interconnect includes a bump.14. A semiconductor device, comprising: a substrate; a passivation layerformed over the substrate; an adhesive layer formed over the passivationlayer; a wetting layer formed over a first portion of the adhesivelayer, the wetting layer not being formed over a second portion of theadhesive layer; and an electrical interconnect formed over the wettinglayer.
 15. The semiconductor device of claim 14, further including abarrier layer formed between the adhesive layer and the wetting layer.16. The semiconductor device of claim 15, wherein the wetting layer,barrier layer and adhesive layer constitute an under bump metallizationstructure.
 17. The semiconductor device of claim 14, further including:a contact pad formed over the substrate; and a redistribution layerformed over the substrate in electrical contact with the contact pad.18. The semiconductor device of claim 14, wherein the first portion ofadhesive layer is removed after the bump is formed.
 19. Thesemiconductor device of claim 14, wherein the electrical interconnectincludes a bump.
 20. A semiconductor device, comprising: a substrate; apassivation layer formed over the substrate; an adhesive layer formedover the passivation layer; a barrier layer formed over a first portionof the adhesive layer, the barrier layer not being formed over a secondportion of the adhesive layer; and an electrical interconnect formedover the barrier layer.
 21. The semiconductor device of claim 20,further including a wetting layer formed over the barrier layer which isover the first portion of the adhesive layer, the wetting layer notbeing formed over the second portion of the adhesive layer.
 22. Thesemiconductor device of claim 21, wherein the wetting layer, barrierlayer and adhesive layer constitute an under bump metallizationstructure.
 23. The semiconductor device of claim 20, further including:a contact pad formed over the substrate; and a redistribution layerformed over the substrate in electrical contact with the contact pad.24. The semiconductor device of claim 20, wherein the first portion ofadhesive layer is removed after the bump is formed.
 25. Thesemiconductor device of claim 20, wherein the electrical interconnectincludes a bump.